1. Field of the Invention
The present invention relates to a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) which is divided into a plurality of banks where memory cells can operate independently of each other, and more particularly to a process of turning on and off column selecting switches for connecting bit lines and data input/output lines with column selecting line signals output from a column decoder.
2. Description of the Related Art
As dynamic RAMS (DRAMS) have in recent years become larger in storage capacity, faster in operation, and lower in power consumption, new specifications including DDR (Double Data Rate), DDR-II, and DDR-III have successively been proposed for higher data transfer rates that are particularly sought after in the art. Under the circumstances, it is a key point in constructing faster DRAMs to shorten column cycles which govern operating speeds in memories.
A conventional structure of a DRAM will be described below with reference to FIG. 1 of the accompanying drawings. FIG. 1 is a block diagram of a 1-Gbit DDR-II SDRAM (Synchronous Dynamic Random Access Memory). The DRAM has a known structure including memory cell array (MCA) 8 comprising a plurality of memory cells, row address buffer XAB, column address buffer XAB, row decoder (XDEC) 6, and column decoder (YDEC) 5 for specifying addresses of memory cell array 8, column selecting lines (YS) 7, column selecting switches (YSW) 80, sense amplifiers (SA) 60 for reading and writing data, main amplifier MA, output buffer DOB, input buffer DIB, control data, main amplifier MA, output buffer DOB, input buffer DIB, control signal buffers RB, CB, WB, and internal voltage generating circuit VG. These components are constructed on a single semiconductor chip by the known semiconductor fabrication technology.
In operation, address signal Ai is supplied from an external source to the DRAM, and row address buffer XAB and column address buffer XAB generate a row address signal and a column address signal, respectively. The row address signal and the column address signal are applied respectively to row decoder 6 and column decoder 5, which select a desired memory cell in memory cell array 8.
Column decoder 5 activates column selecting line 7 corresponding to the column address represented by the supplied column address signal. Column selecting line 7 that is activated by column decoder 5 turns on corresponding column selecting switch 80 to connect a bit line to a local I/O line (LIO).
In a data reading mode, data is sent through sense amplifier 60, local I/O line LIO, main I/O line MIO, a sub-amplifier, and main amplifier MA to read/write bus RWBS, from which data Dout is output through output buffer DOB.
Control signals for the DRAM include row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE that are supplied from an external source through respective buffers RB, CB, WB to the DRAM. Based on the supplied control signals, the DRAM generates internal control signals which control operation of internal circuits of the DRAM. The DRAM has an internal power supply system including internal voltage generating circuit VG which generates various internal voltage levels including a substrate potential, a step-up power supply potential, and a step-down power supply potential in response to external power supply potential VDD and ground potential VSS that are applied from an external source to internal voltage generating circuit VG. The generated internal voltage levels are applied to internal circuits including memory cell array MCA and peripheral circuits thereof.
FIG. 2 of the accompanying drawings shows a conventional structure of memory cell array 8 shown in FIG. 1. FIG. 2 shows a circuit arrangement of two mats divided from a single bank. To these mats, there are connected column selecting lines (YS) 7 from column decoder 5 and mat activating signal lines (RCSEQB) 50 and subword lines SWL from row decoder 6. Mat activating signal lines 50 supply mat activating signals for activating the mats. Each of mat activating signal lines 50 is connected to an inverter 30 which outputs a signal having a logic level inverted from the mat activating signal, as bit line precharging signal (BLEQT) 40. Bit line precharging signal 40 is a control signal for precharging bit lines (BLT, BLB) and controlling common sources in sense amplifiers 601, 602. For stopping precharging the bit lines, bit line precharging signal 40 goes low in level.
Sense amplifiers 601, 602 amplify data that are read to bit lines BLT, BLB. Column selecting switches (YSW) 801 through 804 are connected between sense amplifiers 601, 602 and local I/O lines LIO, and are controlled by column selecting lines (YS) 7.
Operation of the memory cell array shown in FIG. 2 will be described below. It is assumed that data is read from a cell in a left one of the two mats shown in FIG. 2.
When an ACT command for selecting a row address is input, one mat activating signal line (RCSEQB) 50 is selected from the bank address and the row address (XA), making the mat activating signal high in level. Bit line precharging signal (BLEQT) 40 output from inverter 30 goes low in level, allowing a memory cell signal to be read.
When a READ command is then input, one column selecting line 7 is selected by column decoder 5. Four column selecting switches 801 through 804 which are connected to selected column selecting line 7 are turned on, and bit line (BLT, BLB) data are amplified by sense amplifiers 601, 602 and read to local I/O lines LIO.
With the memory cell array of the conventional semiconductor memory device shown in FIG. 2, all four column selecting switches 801 through 804 which are connected to one column selecting line 7 are simultaneously activated. Therefore, if the number of mats controlled by one column selecting line 7 increases, the number of column selecting transistors connected to that one column selecting line 7 also increases, posing a large burden on column selecting line 7, which tends to bring about a signal delay.
To meet demands for lower power consumption, the memory cell array structure shown in FIG. 2 needs to divide bit lines further into a greater number of bit lines for reducing their charging and discharging currents. Conventional semiconductor memory devices with such divided bit lines are disclosed in Japanese laid-open patent publication No. 11-17137, Japanese laid-open patent publication No. 11-126477, and Japanese laid-open patent publication No. 11-185468, for example. If bit lines are divided into a greater number of bit lines, however, since the number of column selecting transistors (YSW) that have to be energized by a single column selecting line (YS) increases, the burden on the column selecting line (YS) further increases, tending to make the signal delay worse.